![]() That encoding is used for special purposes. They're limited in how they may be accessed. Unlike AArch32, the program counter (PC) and the stack pointer (SP) aren't indexed registers. See the Parameter passing section for details on the use of the parameter registers. ![]() 32-bit operations zero-extend their results up to 64 bits. Link Register: Callee function must preserve it for its own return, but caller's value will be lost.Įach register may be accessed as a full 64-bit value (via x0-x30) or as a 32-bit value (via w0-w30). Reserved platform register: in kernel mode, points to KPCR for the current processor In user mode, points to TEB The AArch64 architecture supports 32 integer registers: Register If code could possibly read or write misaligned data from uncached memory, it must make sure to align all accesses.ĭefault layout alignment for locals: Size in bytesĭefault layout alignment for globals and statics: Size in bytes However, accesses to uncached (device) memory still must always be aligned. In an improvement from AArch32, this support now also works for all integer accesses (including multi-word accesses) and for floating-point accesses. Windows running on ARM64 enables the CPU hardware to handle misaligned accesses transparently. Switching endianness is difficult to achieve without kernel mode support in AArch64, so it's easier to enforce. ![]() EndiannessĪs with the ARM32 version of Windows, on ARM64 Windows executes in little-endian mode. To take advantage of these opcodes, apps should first make runtime checks for their existence. ![]() Support for them is currently optional, but recommended. The ARMv8 specification describes new optional crypto and CRC helper opcodes for both AArch32 and AArch64. Both floating-point and NEON support are presumed to be present in hardware. The ARM64 version of Windows presupposes that it's running on an ARMv8 or later architecture at all times. HVA (Homogeneous Short-Vector Aggregate) – A data type with 2 to 4 identical Short-Vector members.HFA (Homogeneous Floating-point Aggregate) – A data type with 2 to 4 identical floating-point members, either floats or doubles.It's aligned to its size, either 8 bytes or 16 bytes, where each element can be 1, 2, 4, or 8 bytes. Short-Vector – A data type directly representable in SIMD, a vector of 8 bytes or 16 bytes worth of elements.There's no such thing as WoA64.įinally, when referring to data types, the following definitions from ARM are referenced: ARM64 – refers to the 64-bit ARM architecture (AArch64).ARM32 – same as ARM, above used in this document for clarity.ARM – refers to the 32-bit ARM architecture (AArch32), sometimes referred to as WoA (Windows on ARM).ARMv8 – the specification of the "8th generation" ARM hardware, which includes support for both AArch32 and AArch64.This version of the ARM hardware is the first version Windows for ARM supported. ARMv7 – the specification of the "7th generation" ARM hardware, which only includes support for AArch32.AArch64 – the new 64-bit instruction set architecture (ISA) defined by ARM.AArch32 – the legacy 32-bit instruction set architecture (ISA) defined by ARM, including Thumb mode execution.With the introduction of 64-bit support, ARM has defined several terms: For more information about the standard ARM EABI, see Application Binary Interface (ABI) for the ARM Architecture (external link). For information about the 32-bit ABI, see Overview of ARM ABI conventions. This article highlights some of the key assumptions and changes from what is documented in the EABI. The basic application binary interface (ABI) for Windows when compiled and run on ARM processors in 64-bit mode (ARMv8 or later architectures), for the most part, follows ARM's standard AArch64 EABI.
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